The invention relates to Digital Data Synthesizers (DDSs) of types that receive digital information representing a desired frequency and produce at the output a cyclical signal having the specified frequency and a preset waveform The desired waveform is stored digitally in advance at successive addresses in a memory. To generate an output signal, a clock establishes sampling times, at each of which a "phase accumulator" generates a greater address. From each address a digital sample value of the desired output waveform is read. The size of address steps at which sample values of the stored waveform are read is changeable, to produce the desired frequency.
For example, many values of a sine function table can be stored in a memory at successive addresses, corresponding to successive phase angles. The storage memory is accessed at a clock-determined sampling rate, with a "staircase-shaped" addressing function. The values of a sine wave are read from the memory, in digital form, at 5-degree steps along the sine function table. The successive sample values that are read out are converted to analog voltages by digital-to-analog converters, (DACs) and the resulting waveform is smoothed by filtering to produce a relatively clean sine wave.
To produce an output at twice the previous frequency, the sample values are taken with the same clock-determined sampling rate as above, but at 10-degree steps along the stored waveform.
A prior art DDS of this type is disclosed in Goldberg's U.S. Pat. No. 4,752,902, issued June 21, 1988, which is incorporated herein by reference. A similar synthesizer is described in Jackson's U.S. Pat. No. 3,735,269, issued May 22, 1973, which is also incorporated herein by reference. The subject is treated generally in an article entitled "A Digital Frequency Synthesizer" published in IEEE Transactions On Audio and Electroacoustics, Volume AU-19, No. 1, March 1971, pages 48-56, and authored by Tierney, et al.